"After evaluating other tools, we chose the VCS solution because of its leading support for verification with SystemVerilog and the high performance of its Native Testbench technology," said Sameer Goyal, principal engineer at Exar. "With the VCS solution, we developed a sophisticated coverage-driven, constrained-random verification environment using SystemVerilog with just four months of effort. This helped us shorten the development cycle down to one third compared with previous projects."

Exar engineers developed a sophisticated SystemVerilog verification environment, using the VCS solution to simulate a complex design, generate randomized stimulus and measure functional coverage. The Exar team was able to quickly learn the SystemVerilog language and create an advanced testbench, which enabled full randomization of many aspects of the environment, from port configuration and the number of ports in the design, to characteristics of the packet and its sub-fields. They also developed a high-level reference model for checking correct design behavior, taking advantage of the VCS solution's support of advanced SystemVerilog language features, including object-oriented programming, classes, functional coverage, arrays, mailboxes and semaphores. Exar was able to quickly find unanticipated corner-case bugs in both the design and reference model by using the VCS solution's powerful constrained- random stimulus generation to create thousands of realistic tests.

"The VCS solution's support for SystemVerilog verification features enables customers like Exar to quickly build and deploy advanced testbenches based on open standards," said Manoj Gandhi, senior vice president and general manager, Verification Group at Synopsys, Inc. "VCS single-compiler technology for design, testbench, assertions and coverage provides higher performance, enabling our customers to verify designs in less time and with higher confidence."

Synopsys Discovery Verification Platform

The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed-signal, system-level verification, assertions, DesignWare(R) verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. Combined with support for industry-standard hardware design and verification languages, including Verilog, VHDL, SystemVerilog, SystemC(TM) and OpenVera(R), and Synopsys' proven Reference Verification Methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.

DesignWare, OpenVera and VCS are registered trademarks of Synopsys, Inc. Discovery is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

    Isela Warner
    Synopsys, Inc.
    650-584-1644
    Email Contact

    Suraya Akbarzad
    Edelman
    650-968-4033
    Email Contact

CONTACT: Isela Warner, Synopsys, Inc., +1-650-584-1644,
Email Contact

Web site: http://www.synopsys.com/